Eurotech ED-C3 02 Especificações descarregar pdf (Página 26)

CPU-71-15 - User Manual

DPD5MAN101

6.2. On-board Jumpers and LEDs

Fig.6 Locations of User Option Jumpers & LEDs

6.2.1. User and Factory Option Jumpers (JPx)

The CPU-71-15 has several user (and factory only) jumpers that are shown in figure 6, above.

Jumper

# of Pins Description

JP1

Clears CMOS and BIOS settings go to default when shunted for 4 seconds while power is off.

Jumper JP1 must not be shunted when power is on.

JP2

JP2 will route BATLOW# to Ground when shunted. JP2 must be left open.

JP3

2 JP3 routes GPI0 to GPO0 when shunted.

JP4

2 JP4 routes GPI1 to GPO1 when shunted.

JP5

2 JP5 routes GPI2 to GPO2 when shunted.

JP6

2 JP6 routes GPI3 to GPO3 when shunted.

JP17

The CPU-71-15 will be hardware initialized to operate as a VMEbus slot 1 bust controller when

JP17 is shunted.

JP18

The CPU-71-15 will be reset by VMEbus resets when JP18 is shunted and JP22 is shunted

between pins 2 & 3.

JP19

The VMEbus SYSRESET generated by the Universe IID on the CPU-71-15 will be routed to the

VMEbus backplane when JP19 is shunted.

JP21

The CPU-71-15 will attempt to boot from an LPC BIOS via connector J29 when JP21 is shunted

and this functionality is not supported. JP21 must be left open.

JP22 3

The VMEbus SYSRESET as generated or received by the Universe IID will reset the CPU-71-15’s

CPU and system resources when JP22 is shunted between pins 2 & 3. Otherwise JP22 must be

shunted between pins 1 & 2.

J6 & J7

18 each

Unpopulated jumper networks for SATA redriver configuring for dual SATA port front panel

connector J2. Default configurations were qualified through testing.

JP1

JP21

JP3

JP22

JP6

JP4

JP5

JP2

JP18

JP17

JP19

D34

D35

D36

D33

D24

LED1

LED2

D25

D32

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 57 58

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Eurotech ED-C3 02 Especificações Página 26

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