Eurotech ED-C3 02 Especificações Página 16

  • Descarregar
  • Adicionar aos meus manuais
  • Imprimir
  • Página
    / 58
  • Índice
  • MARCADORES
  • Avaliado. / 5. Com base em avaliações de clientes
Vista de página 15
CPU-71-15 - User Manual
16
DPD5MAN101
3.3.7. PCI
CPU-71-15 has a 32bit/33MHz PCI bus compliant with the PCI Local Bus Specification Revision 2.3
standard. The PCI bus interface is provided by a PLX PEX8112 bridge that adapts from one (x1) PCI
Express lane off the QM67 and then is used to interface to the Idt Universe IID PCI bus to VMEbus
controller. Additionally it interfaces to the two optional PMC sites. The signal voltage on the PCI bus
is 3.3VDC only.
PCI devices are shown in Table 12.
Table 12. List of PCI devices
Bus
number
Device
number
Function
number
Device
Device model
number
0
0 0 DRAM Controller
Intel
®
Core
TM
i7/i5
1
0 PCI Express Controller 1
Intel
®
Core
TM
i7/i5
1 PCI Express Controller 2
Intel
®
Core
TM
i7/i5
2 PCI Express Controller 3
Intel
®
Core
TM
i7/i5
2 0 Integrated Graphics Device
Intel
®
Core
TM
i7/i5
6 0 PCI Express Controller 4
Intel
®
Core
TM
i7/i5
22
0 Intel
®
Management Engine Interface #1
Intel
®
QM67
1 Intel
®
Management Engine Interface #2
Intel
®
QM67
2 IDE-R
Intel
®
QM67
3 KT
Intel
®
QM67
25 0 Gigabit Ethernet Controller
Intel
®
QM67
26 0 to 7 USB EHCI Controller #2
Intel
®
QM67
27 0 to 7 Intel
®
High Definition Audio Controller
Intel
®
QM67
28
0 PCI Express Port 1
Intel
®
QM67
1 PCI Express Port 2
Intel
®
QM67
2 PCI Express Port 3
Intel
®
QM67
3 PCI Express Port 4
Intel
®
QM67
4 PCI Express Port 5
Intel
®
QM67
5 PCI Express Port 6
Intel
®
QM67
6 PCI Express Port 7
Intel
®
QM67
7 PCI Express Port 8
Intel
®
QM67
29 0 to 7 USB EHCI Controller #1
Intel
®
QM67
30 0 PCI-to-PCI Bridge
Intel
®
QM67
31
0 LPC Controller
Intel
®
QM67
2 SATA Controller #1
Intel
®
QM67
3 SMBus Controller
Intel
®
QM67
5 SATA Controller #2
Intel
®
QM67
6 Thermal Subsystem
Intel
®
QM67
M(*4)
PCI Express
*4M depends on the largest bus number shown on PCI Express.
3.3.8. LPC
CPU-71-15 has a port compliant with the LPC1.1 standard. The LPC bus is used for communication
with the LPC47M107S-MS Super I/O chip. This device is used by the BIOS and provides two COM
ports and an LPT1 port that are accessible from the P2 backplane connector, and a PS/2 port for
mouse and keyboard interfacing that is available from a front panel connector, J28.
Vista de página 15
1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 57 58

Comentários a estes Manuais

Sem comentários