Eurotech ED-C3 02 Especificações descarregar pdf (Página 12)

CPU-71-15 - User Manual

DPD5MAN101

3.1.4. Memory Address Map

Memory space Address Map is shown in Table 2.

Table 2. Memory space Address Map

Device

Address

Lowest 2 GB of Main Memory

0000_0000h

--- 7FFF_FFFFh

PLX PEX8112 PCI Express - PCI Bridge to the

Universe IID VMEbus adapter & the PMC Sites

8000_0000h

--- 9FFF_FFFFh

PCI Express Device

A000_0000h

--- BFFF_FFFFh

Chipset, BIOS, etc

E000_0000h

--- FFFF_FFFFh

Higher 2 GB of DRAM on Cards w/ 4 GB DRAM

1_0000_0000h

--- 1_7FFF_FFFFh

Higher 6 GB of DRAM on Cards w/ 8 GB DRAM

1_0000_0000h

--- 2_7FFF_FFFFh

3.1.5. CPLD Internal Register

CPLD Internal Register is shown in Table 3.

Table 3. CPLD Internal Register map

Address Item

LED Control Register

0000h

3.1.5.1.

Status Register

0001h

3.1.5.2.

Thermal Monitor Select Register

0002h

3.1.5.3.

Thermal Monitor Register

0003h

3.1.5.4.

A CPLD is mounted as internal control logic and for power sequencing. The CPLD’s internal register is

accessible by the LPC bus of 3.3.8 LPC on page 16. Its base address is 0280h.

The register is configured for 8 bits. Both Read (shown below as: R) and Write (shown below as: W)

operations are performed as 8-bit transfers.

R/W : Read and Write

RO : Read only

WO : Write only

3.1.5.1. LED Control Register (offset：0000h)

This register controls LED on CPU-71-15.

Table 4. LED Control Register

bit

Name Meaning Initial Value Access

7..3

RSVD

00000

LED_EN

1：RED/GRN_LED control enabled

0：RED/GRN_LED control disabled

R/W

RED_LED

1：LED (RED) On

0：LED (RED) Off

R/W

GRN_LED

1：LED (GRN) On

0：LED (GRN) Off

R/W

※ LED_EN=’0’ : RED_LED turns on during assertion of the Platform reset that is output by

PCH,while GRN_LED turns on during de-assertion. Please refer to 3.5. LED on page 18 for

further details.

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