Eurotech BRI ISDN Manual do Utilizador descarregar pdf (Página 84)

Am186™CC Microcontroller Router Reference Design User’s Manual

D-8

O U TP U T d t m f 2 o e ; " P I N 1 9 D T M F C h a n n e l 2 o u t p ut e na b le

O U TP U T d t m f 1 o e ; " P I N 2 3 D T MF C h a n ne l 1 ou t p ut e na b le

OUT PU T m c l k 4; " P IN 18 : 4. 0 96 M H z A m 79 C 0 3 1 MCL K i np u t

OUTPUT pclk; "PIN 25: m od ifi ed BCLK signal

" Equations "

"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""

dtmf2oe = pcs5; "inverted pcs5 to create active high OE when tones are

transmitted.

dtmf1oe = pcs4; "inverted pcs4 to create active high OE when tones are

transmitted.

STATE_MACHINE divider CLOCKED_BY mclk_c32 RESET_BY resout;

" This state machine generates 4.096MHz clock signal for the DSLAC.

STATE one:

mclk4=0;

goto two;

STATE two:

mclk4=0;

goto three;

STATE three:

mclk4=1;

goto one;

END divider;

STATE_MACHINE DPLL CLOCKED_BY mclk_c32 RESET_BY resout;

" Jitter reduction circuit, implemented as free running up-counter, that counts 15, 16 or 17

" clock cycles to form a window. The entire circuit can be viewed as a DPLL

STATE one:

pclk=1; " set the PCLK output to one

goto two; " on the next rising edge of the CLK signal go to the next state !

STATE two:

pclk=1;

about.book Page 8 Wednesday, July 21, 1999 11:10 AM

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Eurotech BRI ISDN Manual do Utilizador Página 84